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XC1800 Series of In-System Programmable Configuration PROMs
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September 17, 1999 (Version 1.3)
Preliminary Product Specification
Features
* In-system programmable 3.3V PROMs for configuration of Xilinx FPGAs - Endurance of 10,000 program/erase cycles - Program/erase over full commercial voltage and temperature range IEEE Std 1149.1 boundary-scan (JTAG) support Simple interface to the FPGA; could be configured to use only one user I/O pin Cascadable for storing longer or multiple bitstreams Dual configuration modes - Serial Slow/Fast configuration (up to 15 mHz). - Parallel Low-power advanced CMOS FLASH process 5 V tolerant I/O pins accept 5 V, 3.3 V and 2.5 V signals. 3.3 V or 2.5 V output capability Available in PC20, SO20, PC44 and VQ44 packages. Design support using the Xilinx Alliance and Foundation series software packages. JTAG command initiation of standard FPGA configuration.
Description
Xilinx introduces the XC1800 series of in-system programmable configuration PROMs. Initial devices in this 3.3V family are a 4 megabit, a 2 megabit, a 1 megabit, a 512 Kbit, a 256 Kbit, and a 128 Kbit PROM that provide an easy-to-use, cost-effective method for re-programming and storing large Xilinx FPGA or CPLD configuration bitstreams. When the FPGA is in Master Serial mode, it generates a configuration clock that drives the PROM. A short access time after the rising CCLK, data is available on the PROM DATA (D0) pin that is connected to the FPGA DIN pin. The FPGA generates the appropriate number of clock pulses to complete the configuration. When the FPGA is in Slave Serial mode, the PROM and the FPGA are clocked by an external clock. When the FPGA is in Express or SelectMAP Mode, an external oscillator will generate the configuration clock that drives the PROM and the FPGA. After the rising CCLK edge, data are available on the PROM's DATA (D0-D7) pins. The data will be clocked into the FPGA on the following rising edge of the CCLK. Neither Express nor SelectMAP utilize a Length Count, so a free-running oscillator may be used. See Figure 5 Multiple devices can be concatenated by using the CEO output to drive the CE input of the following device. The clock inputs and the DATA outputs of all PROMs in this chain are interconnected. All devices are compatible and can be cascaded with other members of the family or with the XC1700L one-time programmable Serial PROM family.
CLK CE OE/Reset
* * * *
* * * * * *
TCK TMS TDI TDO
Control and JTAG Interface
Data Memory Address Data
Serial or Parallel Interface
CEO D0 DATA (Serial or Parallel
(Express/SelectMAP) Mode)
D1 - D7 Express Mode and SelectMAP Interface
CF
99020300
Figure 1: XC1800 Series Block Diagram
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Pinout and Pin Description
Table 1: Pin Names and Descriptions Pin Name D0 Boundary Scan Order 4 3 D1 6 5 D2 2 1 D3 8 7 D4 24 23 D5 10 9 D6 17 16 D7 14 13 CLK 0 Function Pin Description 44-pin VQFP 40 44-pin PLCC 2 20-pin SOIC & PLCC 1
DATA OUT D0 is the DATA output pin to provide data for configuring an FPGA in serial mode. OUTPUT ENABLE DATA OUT D0- D7 are the output pins to provide parallel data for configuring a Xilinx FPGA in OUTPUT express mode. ENABLE DATA OUT OUTPUT ENABLE DATA OUT OUTPUT ENABLE DATA OUT OUTPUT ENABLE DATA OUT OUTPUT ENABLE DATA OUT OUTPUT ENABLE DATA OUT OUTPUT ENABLE DATA IN Each rising edge on the CLK input increments the internal address counter if both CE is low and OE/RESET is high.
29
35
16
42
4
2
27
33
15
9
15
7*
25
31
14
14
20
9
19
25
12
43
5
3
20 OE/ RESET 19 18 CE 15
When Low, this input holds the address counter reset and the DATA output at DATA OUT high impedance. OUTPUT ENABLE DATA IN When CE is High, this pin puts the device into standby mode. The DATA output pin is at High impedance, and the device is in low power standby mode.
DATA IN
13
19
8
15
21
10
CF
22 21
DATA OUT Allows JTAG CONFIG instruction to initiate FPGA configuration without powerDATA IN ing down FPGA.
10
16
7*
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Pin Name CEO Boundary Scan Order 13 14 44-pin VQFP 21 44-pin PLCC 27 20-pin SOIC & PLCC 13
Function
Pin Description
DATA OUT Chip Enable (CEO) output is connected to the CE input of the next PROM in the OUTPUT chain. This output is Low when the CE ENABLE and OE/RESET inputs are active AND the internal address counter has been incremented beyond its Terminal Count (TC) value. When the PROM has been read, CEO will follow CE as long as OE/ RESET is High. When OE/RESET goes Low, CEO stays High until the PROM is brought out of reset by bringing OE/RESET High. CEO can be programmed to be either active High or active Low. GND is the ground connection. MODE SELECT The state of TMS on the rising edge of TCK determines the state transitions at the Test Access Port (TAP) controller. TMS has an internal 50K ohm resistive pull-up on it to provide a logic 1 to the device if the pin is not driven. This pin is the JTAG test clock. It sequences the TAP controller and all the JTAG test and programming electronics. This pin is the serial input to all JTAG instruction and data registers. TDI has an internal 50K ohm resistive pull-up on it to provide a logic 1 to the system if the pin is not driven.
GND TMS
6, 18, 28 & 41 5
3, 12, 24 & 34 11
11 5
TCK
CLOCK
7
13
6
TDI
DATA IN
3
9
4
TDO
DATA OUT This pin is the serial output for all JTAG instruction and data registers. TDO has an internal 50k ohm resistive pull-up on it to provide a logic 1 to the system if the pin is not driven. Positive voltage supply of 3.3V for internal logic and input buffers. Positive voltage supply connected to the output voltage drivers.
31
37
17
VCC VCCO
17, 35 & 38 23, 41 & 44 8, 16, 26 & 14, 22, 32 & 36 42
18 & 20 19
*Programmable for Serial Mode only on 18512 and 1801.
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Xilinx FPGAs and Compatible PROMs
Device
XC4003E XC4005E XC4006E XC4008E XC4010E XC4013E XC4020E XC4025E XC4002XL XC4005XL XC4010XL XC4013XL/XLA XC4020XL/XLA XC4028XL/XLA XC4036XL/XLA XC4044XL/XLA XC4052XL/XLA XC4062XL/XLA XC4085XL/XLA XC40110XV XC40150XV XC40200XV XC40250XV XCV50 XCV100 XCV150 XCV200 XCV300 XCV400 XCV600 XCV800 XCV1000
Capacity
Devices 1804 1802 1801 18512 18256 18128 Configuration Bits 4,194,304 2,097,152 1,048,576 524,288 262,144 131,072
Configuration Bits
53,984 95,008 119,840 147,552 178,144 247,968 329,312 422,176 61,100 151,960 283,424 393,632 521,880 668,184 832,528 1,014,928 1,215,368 1,433,864 1,924,992 2,686,136 3,373,448 4,551,056 5,433,888 559,232 781,248 1,041,128 1,335,872 1,751,840 2,546,080 3,608,000 4,715,648 6,127,776
PROM
XC18128 XC18128 XC18128 XC18256 XC18256 XC18256 XC18512 XC18512 XC18128 XC18256 XC18512 XC18512 XC18512 XC1801 XC1801 XC1801 XC1802 XC1802 XC1802 XC1804 XC1804 XC1804 + XC18512 XC1804 + XC1802 XC1801 XC1801 XC1801 XC1802 XC1802 XC1804 XC1804 XC1804 + XC18512 XC1804 + XC1802
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In-System Programming
One or more in-system programmable PROMs can be daisy chained together and programmed in-system via the standard 4-pin JTAG protocol as shown in Figure 2. In-system programming offers quick and efficient design iterations and eliminates unnecessary package handling or socketing of devices. The Xilinx development system provides the programming data sequence using Xilinx JTAG Programmer software and a download cable, a third-party JTAG development system, a JTAG-compatible board tester, or a simple microprocessor interface that emulates the JTAG instruction sequence. All outputs are 3-stated or held at clamp levels during insystem programming.
Reliability and Endurance
Xilinx in-system programmable products provide a minimum endurance level of 10,000 in-system program/erase cycles and a minimum data retention of 10 years. Each device meets all functional, performance, and data retention specifications within this endurance limit.
Design Security
The Xilinx in-system programmable PROM devices incorporate advanced data security features to fully protect the programming data against unauthorized reading. Table 2 shows the security setting available. The read security bit can be set by the user to prevent the internal programming pattern from being read or copied via JTAG. When set it allows device erase. Erasing the entire device is the only way to reset the read security bit. Table 2: Data Security Options Default Read Allowed Program/Erase Allowed Set Read Inhibited via JTAG Erase Allowed
External Programming
Xilinx reprogrammable PROMs can also be programmed by the Xilinx HW-130 device programmer. This provides the added flexibility of using pre-programmed devices in design, boundary-scan manufacturing tools, with an in-system programmable option for future enhancements and design changes.
V CC
GND
(a)
(b)
X5902
Figure 2: In-System Programming Operation (a) solder device to PCB and (b) Program using Download Cable
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IEEE 1149.1 Boundary-Scan (JTAG)
The XC1800 family is fully compliant with the IEEE Std. 1149.1 Boundary-Scan, also known as JTAG. A Test Access Port (TAP) and registers are provided to support all required boundary scan instructions, as well as many of the optional instructions specified by IEEE Std. 1149.1. In addition, the JTAG interface is used to implement in-system programming (ISP) to facilitate configuration, erasure, and verification operations on the XC1800 device. Table 3 lists the required and optional boundary-scan instructions supported in the XC1800. Refer to the IEEE Std. 1149.1 specification for a complete description of boundary-scan architecture and the required and optional instructions. Table 3: Boundary Scan Instructions Boundary- Binary Code Description Scan (7:0) Command Required Instructions BYPASS 11111111 Enables BYPASS SAMPLE/ 00000001 Enables boundary-scan PRELOAD SAMPLE/PRELOAD operation EXTEST 00000000 Enables boundary-scan EXTEXT operation Optional Instructions CLAMP 11111010 Enables boundary-scan CLAMP operation HIGHZ 11111100 3-states all outputs simultaneously IDCODE USERCODE 11111110 11111101 Enables shifting out 32bit IDCODE Enables shifting out 32bit USERCODE
Security field, IR(3), will contain logic 1 if the device has been programmed with the security option turned on; otherwise, it will contain 0. IR(7:5) IR(4) IR(3) IR(2) IR(1:0) ISP TDI-> 0 0 0 Security 0 01 ->TDO Status Note: IR(1:0) = 01 is specified by IEEE Std. 1149.1 Figure 3: Instruction Register values loaded into IR as part of an instruction scan sequence
Boundary Scan Register
The boundary-scan register is used to control and observe the state of the device pins during the EXTEST, SAMPLE/ PRELOAD, and CLAMP instructions. Each output pin on the XC1800 has two register stages that contribute to the boundary-scan register, while each input pin only has one register stage. For each output pin, the register stage nearest to TDI controls and observes the output state, and the second stage closest to TDO controls and observes the 3-state enable state of the pin. For each input pin, the register stage controls and observes the input state of the pin.
Identification Registers
The IDCODE is a fixed, vendor-assigned value that is used to electrically identify the manufacturer and type of the device being addressed. The IDCODE register is 32-bits wide. The IDCODE register can be shifted out for examination by using the IDCODE instruction. The IDCODE register has the following binary format: vvvv:ffff:ffff:aaaa:aaaa:cccc:cccc:ccc1 where v= the die version number f=the family code (50h for XC1800 family) a=the ISP PROM product ID (06h for the XC1804) c=the company code (49h for Xilinx) Note: The LSB of the IDCODE register is always read as logic 1 as defined by IEEE Std. 1149.1 Table 4: IDCODES Assigned to XC1800 devices ISP-PROM XC1801 XC1804 IDCODE 05004093h 05006093h
XC1800 Specific Instructions CONFIG 11101110 Initiates FPGA configuration by pulsing CF pin low
Instruction Register
The Instruction Register (IR) for the XC1800 is 8-bits wide and is connected between TDI and TDO during an instruction scan sequence. In preparation for an instruction scan sequence, the instruction register is parallel loaded with a fixed instruction capture pattern. This pattern is shifted out onto TDO (LSB first), while an instruction is shifted into the instruction register from TDI. The detailed composition of the instruction capture pattern is illustrated in Figure 3. The ISP Status field, IR(4), contains logic 1 if the device is currently in ISP mode; otherwise, it will contain 0. The
Table 4 lists the IDCODE register values for the XC1800 devices.
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The USERCODE instruction gives access to a 32-bit user programmable scratch pad typically used to supply information about the devices's programmed contents. By using the USERCODE instruction, a user-programmable identification code can be shifted our for examination. This code is loaded into the USERCODE register during programming of the XC1800 device. If the device is blank or was not loaded during programming, the USERCODE register will contain FFFFFFFFh. 4-wire Test Access Port (TAP). This simplifies system designs and allows standard Automatic Test Equipment to perform both functions. The AC characteristics of the XC1800 TAP are described as follows.
TAP Timing
Figure 4 shows the timing relationships of the TAP signals. These TAP timing characteristics are identical for both boundary-scan and ISP operations.
XC1800 TAP Characteristics
The XC1800 family performs both in-system programming and IEEE 1149.1 boundary-scan (JTAG) testing via a single
TCKMIN TCK
TMSS
TMSH
TMS
TDIS TDIH
TDI
TDOZX
TDOV
TDOXZ
TDO
Figure 4: Test Access Port Timing
TAP AC Parameters
Table 5 shows the timing parameters for the TAP waveforms shown in Figure 4 Table 5: Test Access Port Timing Parameters (ns) Symbol TCKMIN TMSS TMSH TDIS TDIH TDOZX TDOXZ TDOV Parameter TCK Minimum Clock Period TMS Setup Time TMS Hold Time TDI Setup Time TDI Hold Time TDO Float to Valid Delay TDI Valid to Float Delay TDO Valid Delay Min 100 10 10 15 25 Max
35 35 35
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Controlling Configuration PROMs
Connecting the FPGA device with the configuration PROM. * * * * The DATA output(s) of the of the PROM(s) drives the DIN input of the lead FPGA device. The Master FPGA CCLK output drives the CLK input(s) of the PROM(s). The CEO output of a PROM drives the CE input of the next PROM in a daisy chain (if any). The OE/RESET input of all PROMs is best driven by the INIT output of the lead FPGA device. This connection assures that the PROM address counter is reset before the start of any (re)configuration, even when a reconfiguration is initiated by a VCC glitch. The PROM CE input can be driven from either the LDC or DONE pins. Using LDC avoids potential contention on the DIN pin. If the CE input of the first (or only) PROM can be driven by the DONE output of the first FPGA device, provided that DONE is not permanently grounded. Otherwise, LDC can be used to drive CE, but must then be unconditionally High during user operation. CE can also be permanently tied Low, but this keeps the DATA output active and causes an unnecessary supply current of 10 mA maximum. Express mode is similar to slave serial mode. The DATA is clocked out of the SPROM one byte per CCLK instead of one bit per CCLK cycle. To synchronize with the FPGA the first byte of data is valid 20ns before the second rising edge of CCLK and then on every consecutive CCLK thereafter. Note: When programming in Express mode, to accommodate the 4us set-up time on the INIT pin of the Spartan FPGA, the first line of the configuration stream must not be placed higher than the 3C byte address of the PROM.
either automatically upon power up, or on command, depending on the state of the three FPGA mode pins. In Master Serial mode, the FPGA automatically loads the configuration program from an external memory. Xilinx PROMs are designed for compatibility with the Master Serial mode. Upon power-up or reconfiguration, an FPGA enters the Master Serial mode whenever all three of the FPGA modeselect pins are Low (M0=0, M1=0, M2=0). Data is read from the PROM sequentially on a single data line. Synchronization is provided by the rising edge of the temporary signal CCLK, which is generated during configuration. Master Serial Mode provides a simple configuration interface. Only a serial data line and two control lines are required to configure an FPGA. Data from the PROM is read sequentially, accessed via the internal address and bit counters which are incremented on every valid rising edge of CCLK. If the user-programmable, dual-function DIN pin on the FPGA is used only for configuration, it must still be held at a defined level during normal operation. The Xilinx FPGA families take care of this automatically with an onchip default pull-up resistor.
*
*
Programming the FPGA With Counters Unchanged Upon Completion
When multiple FPGA-configurations for a single FPGA are stored in a PROM, the OE/RESETpin should be tied Low. Upon power-up, the internal address counters are reset and configuration begins with the first program stored in memory. Since the OE/RESETpin is held Low, the address counters are left unchanged after configuration is complete. Therefore, to reprogram the FPGA with another program, the DONE line is pulled Low and configuration begins at the last value of the address counters. This method fails if a user applies OE/RESET during the FPGA configuration process. The FPGA aborts the configuration and then restarts a new configuration, as intended, but the PROM does not reset its address counter, since it never saw a High level on its OE input. The new configuration, therefore, reads the remaining data in the PROM and interprets it as preamble, length count etc. Since the FPGA is the master, it issues the necessary number of CCLK pulses, up to 16 million (224) and DONE goes High. However, the FPGA configuration will be completely wrong, with potential contentions inside the FPGA and on its output pins. This method must, therefore, never be used when there is any chance of external reset during configuration.
Initiating FPGA Configuration
The XC1800 devices incorporate a pin named CF that is controllable through the JTAG CONFIG instruction. Executing the CONFIG instruction through JTAG will pulse the CF low for 300-500ns, which will reset the FPGA and initiate configuration. The CF pin must be connected to the PROGRAM pin on the FPGA to use this feature.
Selecting Configuration Modes
The XC1800 accommodates serial and parallel methods of configuration. The configuration modes are selectable through a user control register in the XC1800 device. This control register is accessible through JTAG, using the Xilinx JTAG Programmer software.
Cascading Configuration PROMs
For multiple FPGAs configured as a daisy-chain, or for FPGAs requiring larger configuration memories, cascaded PROMs provide additional memory. Multiple XC1800 devices can be concatenated by using the CEO output to drive the CE input of the following device. The clock inputs and the data outputs of all XC1800 devices in the chain are
FPGA Master Serial Mode Summary
The I/O and logic functions of the Configurable Logic Block (CLB) and their associated interconnections are established by a configuration program. The program is loaded 8
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XC1800 Series of In-System Programmable Configuration PROMs
interconnected. After the last bit from the first PROM is read, the next clock signal to the PROM asserts its CEO output Low and disables its DATA line. The second PROM recognizes the Low level on its CE input and enables its DATA output. See Figure 5. After configuration is complete, the address counters of all cascaded PROMs are reset if the PROM OE/RESET pin goes Low. To reprogram the FPGA with another program, the DONE line goes Low and configuration begins where the address counters had stopped. In this case, avoid contention between DATA and the configured I/O use of DIN.
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XC1800 Series of In-System Programmable Configuration PROMs
Vcc
DOUT
OPTIONAL Daisy-chained FPGAs with Different Configurations OPTIONAL Slave FPGAs with Identical Configurations Vcc Vcco
FPGA
MODES
DIN CCLK DONE INIT PROGRAM
DATA
VCC
VCCO
DATA CLK CE OE/RESET Cascaded PROM
CLK FIRST CE PROM CEO OE/RESET CF
(Low Resets the Address Pointer)
Master Serial Mode
3.3V M0 M1 M2 NC CS WRITE VIRTEX Select MAP DONE CCLK D0-D7 INIT
4.7k
I/O* I/O*
Vcc
Vcco
4.7k
BUSY
External Osc 3.3V VCC 4.7K
VCCO
XC18xx
CLK
8
PROGRAM
D0-D7 CE OE/RESET
CEO CF
Virtex Select MAP Mode
Vcc Vcc Vcco CS1 Vcc
4k
M0
M1 DOUT CS1
M0
M1 DOUT
To Additional Optional Daisy-Chained Devices
Spartan XL
D0-D7 PROGRAM INIT CCLK DONE
VCC CEO CE
VCCO D0-D7
CF
Optional Daisy-Chained Spartan XL
D0-D7 PROGRAM INIT CCLK
8
XC18xx
DONE
OE/RESET CLK
CCLK
To Additional Optional Daisy-Chained Devices
Spartan XL Express Mode
*CS and WRITE must be pulled down to be used as I/O. One option is shown.
Figure 5: (a) Master Serial Mode (b) Virtex Select MAP Mode (c) Spartan XL Express Mode
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5V Tolerant I/Os
The I/Os on each re-programmable PROM are fully 5V tolerant even through the core power supply is 3.3 volts. This allows 5V CMOS signals to connect directly to the PROM inputs without damage. In addition, the 3.3V VCC power supply can be applied before or after 5V signals are applied to the I/Os. In mixed 5V/3.3V/2.5V systems, the user pins, the core power supply (VCC), and the output power supply (VCCO) may have power applied in any order. This makes the PROM devices immune to power supply sequencing issues.
pulse from the FPGA. OE/RESET is connected to an external resistor to pull OE/RESET HIGH releasing the FPGA INIT and allowing configuration to begin. OE/RESET is held low until the XC1800 voltage reaches the operating voltage range. If the power drops below 2.0 Volts, the PROM will reset.
Standby Mode
The PROM enters a low-power standby mode whenever CE is asserted High. The output remains in a high impedance state regardless of the state of the OE input. JTAG pins TMS, TDI and TDO can be 3-state or high.
Reset Activation
On power up, OE/RESET is held low until the XC1800 is active (1ms) and able to supply data after receiving a CCLK Table 6: Truth Table for PROM Control Inputs Control Inputs Internal Address OE/RESET Low High Low High CE Low Low High High if address < TC: increment if address > TC: don't change Held reset Held reset Held reset DATA active 3-state 3-state 3-state 3-state CEO High Low High High High Icc active reduced active standby standby Outputs
Note: TC = Terminal Count = highest address value. TC+1 = address 0.
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Absolute Maximum Ratings
Symbol VCC VIN VTS TSTG TSOL TJ Description Supply voltage relative to GND Input voltage with respect to GND Voltage applied to 3-state output Storage temperature (ambient) Maximum soldering temperature (10 s @ 1/16 in.) Junction Temperature Value -0.5 to +4.0 -0.5 to +5.5 -0.5 to +5.5 -65 to +150 +260 +150 Units V V V C C C
Notes Maximum DC undershoot below GND must be limited to either 0.5V or 10mA, whichever is easier to achieve. During 1:
2: transitions, the device pins may undershoot to -2.0V or overshoot to +7.0V, provided this over- or undershoot lasts less then 10 ns and with the forcing current being limited to 200mA. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability.
Recommended Operating Conditions
Symbol VCCINT Commercial Industrial VCCO Parameter Internal Voltage supply (TA = 0C to +70C) Internal Voltage supply (TA = -40C to +85C) Min 3.0 3.0 3.0 2.3 0 2.0 0 Max 3.6 3.6 3.6 2.7 0.8 5.5 VCCO Units V V V V V V V
Supply voltage for output drivers for 3.3V operation Supply voltage for output drivers for 2.5V operation
VIL VIH VO
Low-level input voltage High-level input voltage Output voltage
Quality and Reliability Characteristics
Symbol tDR NPE VESD Data Retention Program/Erase Cycles (Endurance) Electrostatic Discharge (ESD) Description Min 10 10,000 2,000 Max Units Years Cycles Volts
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DC Characteristics Over Operating Conditions
Symbol VOH Parameter High-level output voltage for 3.3 V outputs High-level output voltage for 2.5 V outputs VOL Low-level output voltage for 3.3V outputs Low-level output voltage for 2.5V outputs ICCA ICCS1 ICCS2* ICCS3** IILJ IIL IIH CIN & COUT Supply current, active mode Supply current, standby mode 1 Supply current, standby mode 2 Supply current, standby mode 3 JTAG pins TMS, TDI, and TDO Input leakage current Input & Output high-Z leakage current Input and Output Capacitance VCC = MAX VIN = GND VCC = Max VIN = GND or VCC VCC = Max VIN = GND or VCC VIN = GND f = 1.0 MHz -100 -10.0 -10.0 10.0 10.0 10.0 Test Conditions IOH = -4 mA IOH = -500 A IOL = 8 mA IOL = 500 A at maximum frequency Min 2.4 90% VCCO 0.4 0.4 30.0 2.0 300 100 Max Units V V V V mA mA A A A A A pF
* 1801/18512/18256/18128 only, cascadable **1801/18512/18256/18128 only, non-cascadable
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.AC
Characteristics Over Operating Conditions
CE 9 TSCE 9 TSCE 10 THCE
RESET/OE TLC 7 CLK TOE 2 DATA 4 TOH
99020801
8 THC
6 TCYC
11 THOE
1
3 TCAC
4 TOH
5 TDF
TCE
1 2 3 4 5 6 7 8 9 10 11
Symbol TOE TCE TCAC TOH TDF TCYC TLC THC TSCE THCE THOE
Description OE to Data Delay CE to Data Delay CLK to Data Delay Data Hold From CE, OE, or CLK CE or OE to Data Float Delay2 Clock Periods CLK Low Time3 CLK High Time3 CE Setup Time to CLK (to guarantee proper counting) CE Hold Time to CLK (to guarantee proper counting) OE Hold Time (guarantees counters are reset)
Min
Max 30 45 45 50
0 67 25 25 25 0 25
Units ns ns ns ns ns ns ns ns ns ns ns
Notes: 1. AC test load = 50 pF
2. Float delays are measured with 5 pF AC loads. Transition is measured at +/- 200mV from steady state active levels. 3. Guaranteed by design, not tested. 4. All AC parameters are measured with VIL = 0.0 V and VIH = 3.0 V.
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AC Characteristics Over Operating Condition When Cascading
RESET/OE
CE
CLK 12 TCDF DATA Last Bit 13 TOCK CEO 14 TOCE 14 TOCE
99020800
First Bit 15 TOOE
Symbol 12 13 14 15 TCDF TOCK TOCE TOOE
Description CLK to Data Float Delay2, 3 CLK to CEO Delay3 CE to CEO Delay3 RESET/OE to CEO Delay
3
Min
Max 50 30 35 30
Units ns ns ns ns
Notes: 1. AC test load = 50 pF
2. Float delays are measured with 5 pF AC loads. Transition is measured at +/- 200mV from steady state active levels. 3. Characterized but not 100% tested. 4. All AC parameters are measured with VIL = 0.0 V and VIH = 3.0 V.
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XC1800 Series of In-System Programmable Configuration PROMs
Ordering Information XC1804 VQ44 C
Device Number
XC1804 XC1802 XC1801 XC18512 XC18256 XC18128
Operating Range/Processing C = Commercial (TA = 0 to +70C) Package Type
VQ44=44-Pin Plastic Quad Flat Package PC44=44-Pin Plastic Chip Carrier SO20=20-Pin Small-Outline Package PC20=20-Pin Plastic Leaded Chip Carrier I = Industrial (TA = -40 to +85C)
Valid Ordering Combinations
XC1804VQ44C XC1804PC44C XC1804VQ44I XC1804PC44I XC1802VQ44C XC1802PC44C XC1802VQ44I XC1802PC44I XC1801SO20C XC1801PC20C XC1801SO20I XC1801PC20I XC18512SO20C XC18512PC20C XC18512SO20I XC18512PC20I XC18256SO20C XC18256PC20C XC18256SO20I XC18256PC20I XC18128SO20C XC18128PC20C XC18128SO20I XC18128PC20I
Marking Information
44-Pin Package Device Number
XC1804 XC1802
XC1804 VQ44 C
Operating Range/Processing Package Type
VQ44=44-Pin Plastic Quad Flat Package PC44=44-Pin Plastic, Leaded Chip Carrier C = Commercial (TA = 0 to +70C) I = Industrial (TA = -40 to +85C)
20-Pin Package Device Number
XC1801 XC18512 XC18256 XC18128
1801 S C
Operating Range/Processing Package Type
S=20-Pin Small-Outline Package J=20-Pin Plastic Leaded Chip Carrier C = Commercial (TA = 0 to +70C) I = Industrial (TA = -40 to +85C)
Revision Control
Date 2/9/99 8/23/99 9/1/99 9/16/99 Version 1.0 1.1 1.2 1.3 Revision First publication of this early access specification Edited text, changed marking, added CF and parallel load Corrected JTAG order, Security and Endurance data. Corrected SelectMAP diagram, control inputs, reset polarity. Added JTAG and CF description, 256 Kbit and 128 Kbit devices. September 17, 1999 (Version 1.3)
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